Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs

In this paper, we model and synthesis a high speed Arithmetic inverse square root, square root, and division (ISD) unit based on existing algorithms similar to the unit in [3]. With area/speed tradeoff limitation, our concentration was on designing high speed Arithmetic units with moderate area increase. Our concentration on the (ISD) unit using digit recurrence algorithms led to the modeling of a robust unit, sharing the same recurrence and same hardware to perform all three operations. Minor differences occur in the initialization stage and number of iterations and final rounding. Synthesis tools were used to evaluate our model and reports showed that our ISD unit has a minimum path delay of 12.443ns. Area was moderate and within range when theoretically comparing three separate units to complete the three operations. We further decrease the latency of the ISD unit by modeling short fast adder in the critical path.